Lock detector for phase locked loops

ABSTRACT

A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of application Ser. No.10/435,446, filed May 9, 2003, which is a divisional of application Ser.No. 09/794,310, filed Feb. 27, 2001 (now U.S. Pat. No. 6,580,328), whichis a continuation of application Ser. No. 09/433,811, filed Nov. 3, 1999(now U.S. Pat. No. 6,211,742), which claimed the benefit of provisionalApplication No. 60/107,104, filed Nov. 4, 1998, the entire contents ofwhich are incorporated fully herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates generally to lock detectors forphase lock loops and, more particularly, to a lock detector whichestablishes upper and lower bounds to a lock range in order to ensurethat phase error is substantially confined within the range beforeacquisition of lock is declared.

BACKGROUND OF THE INVENTION

[0003] Phase lock loops (PLLs) and clock recovery circuits (CRCs) havefound wide application in such diverse areas as digital communicationsystems, wireless systems, digital circuits and data recovery systemsfor use in connection with mass storage media such as hard disk, tapeand optical drives. In the field of digital communication systems, phaselock loops are typically used in modern digital communications receiversto recover useful data from a transmission signal stream by providingdata recovery circuitry with a timing reference having the appropriatefrequency and phase characteristics so as to match timingcharacteristics of the transmitted signal and thus, ensure proper datarecovery.

[0004] In modern HDTV signal transmissions, a receiver must be capableof locking onto a transmitter's pilot carrier phase as well as thetransmitter's timing phase. Locking the receiver to the transmitter'scarrier phase is commonly referred to as carrier phase recovery, whereaslocking onto the timing phase of the transmitter is referred to astiming phase recovery. Both of these functions are critical to a modernday communications system since the receiver must be synchronized to thetransmitter in order that transmitted data may be correctly demodulated,and equalized.

[0005] Applications of phase lock loops (or more correctlyfrequency-phase locked loops, FPLLs) in a modern high-speedcommunications system would include their use as frequency acquisitiontools in a receiver's channel tuner and as an automatic gain control(AGC) loop, disposed within a channel tuner, which ensures that thepower level of a received signal is suitably limited to a particulardesired level. Thus, it can be seen that PLLs and FPLLs play asignificant role in the effective operation of various portions of amodern digital communication system. Indeed, it is difficult to conceiveof a modern high-speed digital communications system that does not makeextensive use of precision PLLs.

[0006] Notwithstanding the necessity of their use in moderncommunication systems, conventional PLLs suffer from a particulardisadvantage that makes their use in modern, high-speed communicationsystems problematic. This disadvantage relates most particularly to thetime characteristics of the phase error response of a first order orsecond order PLL in response to a prompt change in the phase of an inputsignal. Given the extremely precise phase and timing alignments requiredin modern high-speed communication systems, and their correspondinglysmall phase error margins, a false designation of phase lock during aphase acquisition procedure can very easily result in the loss of systemtiming and a consequent disruption of, for example, carrier recoveryoperations and thus, a loss of signal.

SUMMARY OF THE INVENTION

[0007] The present invention is directed to a system and method forevaluating phase detector output so as to optimally determine when phaselock has been achieved. The novel lock detection system is suitable forincorporation in a phase locked loop of the type including a phasedetector configured to develop phase error signals for use by, forexample, a loop filter in deriving control signals for an oscillatorcircuit. A lock detector circuit evaluates phase error signals in orderto determine whether a locked condition has been achieved on the basisof the output signal train of phase detector's passing evaluationagainst a magnitude metric and a timing metric.

[0008] In one aspect of the invention, the lock detector circuitincludes a summing circuit having at least one input for receiving phaseerror signals developed by the phase detector. The summing circuitcombines the absolute value of an input phase error signal with anegative valued first limit signal which corresponds to the maximumallowable phase error during lock. Summation of the two signals givesrise to a negative-valued signal when the phase error signal is belowthe first limit and a positive-valued signal when the absolute magnitudeof the input phase error signal is above the first limit.

[0009] The output of the summing circuit is compared to a zero referencesignal and outputs in a first state when the summation result is lessthan zero and outputs a signal in a second state when the summationresult is greater than zero. A summation result less than zero indicatesthat the absolute magnitude of an input phase error signal is less thanthe first limit signal and therefore converging toward zero.

[0010] In a further aspect of the invention, the comparison circuitsignal in a first state initiates a time interval counter. The timeinterval counter is reset at any time the absolute magnitude of anyphase error signal exceeds the first limit signal, i.e., at any time thesummation result is greater than or equal to zero. Lock is declaredafter the time interval counter counts to the end of a specified timeinterval. Thus, phase error signals must not only converge to a valueless than the first limit signal but also remain at a value below thefirst limit signal for a period of time equal to the time intervalcounter's specified time interval.

[0011] In an additional aspect of the invention, a low pass filter iscoupled between the lock detector and the phase detector circuit. Thelow pass filter averages phase error component values to removeextraneous high frequency noise and improve system performance. Theoutput of the low pass filter is coupled to a conditioning circuit, suchas a rectification circuit, which receives input phase error signalscorresponding to both positive and negative phase relationships andconditions the phase error signal such that the output of theconditioning circuit represents their absolute magnitude.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] These and other features, aspects and advantages of the presentinvention will be more fully understood when considered with respect tothe following detailed description, appended claims and accompanyingdrawings wherein:

[0013]FIG. 1(a) is a semi-schematic block level diagram of aconventional phase lock loop (PLL) system used for data recovery,according to the prior art;

[0014]FIG. 1(b) is a waveform diagram illustrating the frequency andphase error response of the PLL of FIG. 1(a) to an input frequency step;

[0015]FIG. 2 is a waveform diagram illustrating the time response of PLLphase error to a phase step, including the extent of ambiguous lockregions as a function of phase error margin reduction, and indicatingthe lock acquisition to lock declaration timing window in accordancewith practice of principles of the invention;

[0016]FIG. 3 is a semi-schematic simplified block diagram of a lockdetector for optimally detecting a true lock condition in accordancewith the present invention; and

[0017]FIG. 4 is a semi-schematic simplified block diagram of a phaselock loop architecture incorporating the lock detector of FIG. 3 inaccordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0018] Conceptually, a conventional phase lock loop (PLL), such asdepicted in semi-schematic block diagram form in FIG. 1(a), is afeedback system that operates on the excess phase of nominally periodicsignals. Implementation of such a PLL normally comprises a phasedetector (PD) or phase and frequency detector (PFD) 10 whose output iscoupled to a loop filter (low-pass filter or LPF) 12 which, in turn,drives some means for generating a synchronous clock signal 14, such asa voltage controlled oscillator (VCO), current controlled oscillator(CCO) or decision controlled oscillator (DCO). When receiving data,during what is conventionally termed frequency or velocity lock, theoscillation frequency of the clock signal generator (termed a VCO forconvenience) is determined by, and locked to the frequency of anexternal periodic signal source provided for such purpose (not shown),just prior to receiving an input datastream. Once frequency or velocitylock is established, the VCO runs in what might be termed aquasi-flywheel mode at a mean frequency determined during velocity lock.

[0019] Subsequent correction control to the VCO frequency is developedby phase-locking a transition edge of the synchronous VCO signal to atransition edge of an incoming data signal. The VCO is phase-locked tothe incoming serial data stream by comparing the phase of the risingedge of the VCO clock signal FIG. 1 to the phase of the rising edge ofdata in the phase detector 10. A phase or time difference detectedbetween the two rising edges causes the phase detector to issue a signalproportional to the phase difference which directs the VCO to eitherspeed-up or slow-down in response to phase variations in the datastream.

[0020] Conventionally, the phase detector incorporates logic circuitry(in effect a logical NOR function) which precludes an output signal frombeing issued during phase comparisons unless two phase edges are presentduring a particular comparison cycle. This features prevents the PLLfrom becoming unstable by trying to perform a phase comparison between aVCO rising edge and a, for example, data ZERO bit (a data signalnecessarily without a rising edge).

[0021] The loop filter 12 averages the phase-lead and/or phase-lagpulses from the phase detector 10, to define a control voltage which isapplied to the input of the VCO 14 and further functions as a low-passfilter in order to minimize the effects of random component generatednoise and certain forms of high frequency jitter. It is common practiceto low-pass filter the difference component of a pair of PD samplesignals to reduce the effect of random noise on the system.

[0022] Once phase lock is established, the output of the VCO 14 definesa timing signal which is provided as a clock input to a data recoverycircuit, or decision circuit, 16. The overall effect is to define astandardized, unipolar timing signal coincident with every transition ofthe input data, such that the data recovery circuit or decision circuit16 is able to provide properly regenerated data.

[0023] In such a system as depicted in FIG. 1(a), data recoveryoperations are necessarily precluded until such time as the PLL hasachieved an adequate phase lock within the phase error budget of theoverall system. Acquisition of lock is typically determined by a controllogic block incorporating lock detection circuitry which might bedisposed between the phase detector 10 and loop filter 12, in parallelwith the filter or, might be disposed within the loop filter itself.Lock detectors conventionally operate by evaluating the phase detectoroutput pulse width (or pulse duration) which is in turn, proportional tothe phase error between an incoming signal and the VCO pulse train. Lockis declared by comparing the phase detector output pulse width to apre-established threshold level which is commonly defined by the upperbound of the allowable phase error of the system. When the pulsedetector output pulse width meets or falls below the phase errorthreshold, the system is deemed to have acquired lock and a lock signalis commonly asserted to the data recovery circuit 16, thereby enablingdata recovery operations to proceed.

[0024] As shown in FIG. 1(b), when a PLL obtains lock following a changein the input frequency ω_(in) the phase error φ_(e) typically convergesto a limit value, in most cases having a mean limit value of zero, asthe frequency ω_(out) of the VCO 14 converges to the input value. Inthese particular circumstances, phase error is often observed to ditherabout the mean zero value. In certain other cases, a PLL is able toattain lock, but the phase error exhibits a small non-zero mean value.This particular circumstance occurs whenever the phase of the inputsignal exhibits a rapid change. The cause of these phenomena will becomeapparent when it is recognized that a first order PLL is defined asbeing capable of achieving phase lock with zero phase error to a givenstep change in the phase of the input signal. This same first order PLLis capable of achieving phase lock with a non-zero phase error to alinear ramp in the phase of an input signal. Similarly, a second orderPLL is typically understood as being capable of achieving phase lockwith zero phase error to either a step or a ramp in the phase of aninput signal, while the same second order PLL is capable of achievingphase lock with a non-zero phase error to a parabolic phase change ofthe input signal.

[0025] A time domain plot of output frequency change and phase errorwith respect to time in response to a prompt input frequency change isdepicted in the waveform diagram of FIG. 1(b). It will be understood, bythose with skill in the art, that some degree of frequency response lagand system damping related ringing characteristics are exhibited by allnon-ideal control systems in response to prompt input perturbations.Accordingly, some degree of phase error will necessarily attend suchprompt input changes.

[0026]FIG. 2 is a waveform diagram illustrating a time plot of phaseerror associated with a prompt input change, such as might result from afrequency step. In the diagram, phase error in radians is plotted as afunction of time immediately following a prompt phase change at thephase detector input. For purposes of convenience, only the positiveportion of the phase plane is depicted in FIG. 2. It will be understoodthat a mirror image phase response (corresponding to a phase lag) isalso susceptible of illustration but with opposite signs. As illustratedin the figure, the PLL achieves lock whenever the phase error convergesbelow a certain pre-determined absolute limit, denoted in FIG. 2 as“limit 1”. As is also clear from FIG. 2, if the phase error margin, asdefined by “limit 1”, is made particularly small, it is quite possiblefor the phase error to fall below the lock limit for a brief period oftime, and then exceed the lock limit, in the opposite direction, for asubstantial time duration before the system settles and the phase errorconverges closer to the zero limit. Accordingly, it will be understoodthat simply evaluating phase error against a particular limit value isan insufficient condition to initiate lock declaration and begin datarecovery operations since this could very easily result in a false lockcondition when the phase error response characteristic exceeds thedesired limit in the opposite direction.

[0027] It is, therefore, necessary to introduce a second limitcondition, denoted “limit 2” herein which defines a time interval withinwhich the phase error response characteristic must remain within thepre-determined “limit 1”, in order to achieve lock.

[0028] As can be seen from inspection of FIG. 2, phase lock, within theerror margin, is actually achieved at the point where the phase errorresponse characteristic reenters the “limit 1” boundary and remainswithin the boundary, although oscillating periodically about the zeroradians point. This “lock achieved” position is indicated in the diagramof FIG. 2 at 20 and represents the third crossing of the “limit 1”boundary by the phase error response characteristic. It will be seenthat the phase response characteristic passes through the “limit 1”boundaries during a first time interval t1 which is of generally shortduration. The phase error response characteristic then passes outsidethe “limit 1” boundary, falls to its maximum lag value and againapproaches and crosses the “limit 1” boundary during a second timeinterval t₂, following which it remains within the “limit 1” boundariesfor the remainder of the time interval of interest. In accordance withthe present invention, the indication of “lock achieved” is thereforedelayed until a period of time, exceeding “limit 2”, has passed duringwhich period of time the signal remains within “limit 1”, as shown inFIG. 2 at 21. At this time, lock may be declared.

[0029] State trajectories and transient response characteristics ofphase lock loops may be determined by simulation, once the designparameters of a particular PLL have been established. Accordingly, aphase error response plot, such as illustrated in FIG. 2, can bedeveloped for various PLL types, as well as other phase responsedependent control systems, from which appropriate “limit 2” time periodsmay be extracted by numerical or graphical interpretation. In theexample of FIG. 2, an appropriate “limit 2” time period would be a timeinterval that necessarily exceeded t1 in order to ensure that the falselock position depicted therein does not trigger a lock achievedcondition. Rather, as depicted in FIG. 2, a significantly longer “limit2” duration would ensure that the phase error response characteristicremained within the “limit 1” boundaries prior to lock being declaredand data recovery operations commenced.

[0030] A particular, exemplary hardware implementation of such a novellock detector is illustrated in semi-schematic simplified block diagramform in FIG. 3. Phase error signals, developed by a phase detector arereceived at the input of a low-pass filter 22 which performs the samehigh frequency noise reduction function as the loop filter (12 ofFIG. 1) of a conventional PLL. The low pass filter 22 averages the phaseerror received at the input and provides the averaged error signal to asignal conditioning or shaping circuit, such as a digital rectificationcircuit 24, which functions, in the illustrated embodiment, to redefinethe average phase error in terms of its absolute value. In other words,phase-lag error is converted into phase-lead error terms in order thatthe phase error terms have the appropriate sign for subsequentsubtractive combination with a user pre-defined, non-zero DC “limit 1”value in an arithmetic computation circuit, such as a summing amplifier26.

[0031] Once the absolute value of the phase error has been subtractivelysummed with the “limit 1” value, the resulting signal is processed by acomparator circuit 28 which compares the residual magnitude to asuitable reference value, such as zero, in order to determine if thephase error magnitude exceeds “limit 1” or is within the “limit 1”boundaries, i.e., the absolute magnitude of the phase error is greaterthan or less than the absolute magnitude of the “limit 1” value.Depending on the comparison results, if the absolute phase errormagnitude is below “limit 1” the comparator circuit 28 may initiate atiming circuit, such as an interval counter 30, which begins to count-upas soon as the phase error magnitude falls below “limit 1”. The outputof the interval counter 30 is compared to a user defined time intervallimit, “limit 2” in comparison logic 32 and when the interval countervalue reaches the “limit 2” value, the system is deemed to have acquiredlock and “lock” is declared to a data recovery circuit, for example.

[0032] In the event that the phase error magnitude falls within the“limit 1” boundary and then subsequently exceeds the “limit 1”threshold, the comparator 28 deasserts the interval counter and resetsthe interval counter to zero in anticipation of the phase error's againpassing through the “limit 1” boundary.

[0033] A novel lock detector, such as described in connection with theillustrated embodiment of FIG. 3, may be easily incorporated into aphase lock loop of the type suitable for carrier recovery operations ina high-speed digital communication system. With amplitude modulationtransmission schemes, the phase shift imposed by the modulating signalis relatively constant and a simplified PLL such as depicted in FIG. 1,might be used to detect the phase difference between the recoveredcarrier and the internal frequency reference of the receiver. Suchsimplified systems are not efficient for use in conjunction with phaseor quadrature modulation transmission schemes, due to the variation inthe carrier phase imposed by the encoded intelligence (data). Inaddition, the frequency uncertainty of typical RF oscillators used in upand down conversion processes are often greater than the affordable PLLbandwidth imposed by low phase jitter requirements. One possiblesolution to the bandwidth problem, in accordance with the presentinvention, is to change the characteristics of the loop filter by, forexample, switching between two such loop filters, to accommodate thedivergent requirements.

[0034] A wide PLL bandwidth might be used during the initial acquisitionprocess and then a narrow PLL bandwidth invoked once lock has beenachieved. Such a system, in effect, would comprise two loop filters, anda logical switch, configured to select between the two filters once thephase error signal was determined to be sufficiently small, i.e., oncelock had been achieved.

[0035] In FIG. 4, such an exemplary PLL system is depicted. The PLL ofFIG. 4 suitably comprises a phase detector (PD) 34, configured toevaluate the phase relationship between a reference signal, i.e., a datasignal, and the output of a VCO 36. Phase error signals are directed toone or the other of two loop filters, a wideband filter 37 and a narrowband filter 38, by operation of a switch 39. Each of the loop filters 37and 38 develops a control signal in conventional fashion suitable foradvancing or retarding the frequency characteristics (and thus phase) ofthe VCO 36. The output of the PD 34 is also coupled in parallel fashionwith the switch 39 to a lock detector 40 constructed and operating inaccordance with the embodiment illustrated in connection with FIG. 3.The lock detector 40 functions to evaluate the phase error response ofthe PD 34 and determine the appropriate phase error conditions underwhich optimal phase lock occurs. Once phase lock is achieved, i.e., boththe “limit 1” and “limit 2” conditions have been met, the lock detector40 asserts a “lock” signal to a decision engine 42 such as switchcontrol logic, or directly to the switch. In response, the systemswitches the PD output from the wideband filter to the narrow bandfilter, adaptively reconfiguring the PLL bandwidth as a consequence. ThePLL output is now optimally configured for data recovery operations suchas coherent demodulation.

[0036] A novel lock detector circuit has been described that operates tooptimally detect phase lock by evaluating phase error as a function twometrics; a magnitude metric and a time metric. The lock detector notonly determines when a phase detector's phase error responsecharacteristic crosses a nominal minimum error threshold, but alsodefines a nominal time interval within which the phase error must remainbelow the nominal threshold value, in order that a lock condition may bedeclared. The lock detector functions by recognizing that immediatelyafter the occurrence of an input phase or frequency step, the phaseerror response characteristic of a PLL may actually pass through theerror threshold boundaries and consequently exhibit an instantaneousphase error less than the error threshold for a brief period of timebefore true lock is actually achieved.

[0037] While the invention has been described in terms of particularcomponents arranged in a particular fashion, it will be evident to onehaving skill in the art that the invention might likewise be suitablyimplemented with a different component arrangement. In particular, the“limit 1” summing amplifier and zero level comparator components may becombined into a comparator circuit that directly compares the absolutevalue of a phase error to a user defined “limit1” threshold value. Fromthe foregoing, it will be evident to those having skill in the art thatthe particular component descriptions and arrangements contained in theillustrated embodiments are solely for purposes of explanation and thatthe invention is not limited to the particular embodiments orarrangements disclosed. Nor is the invention intended to be limited tothe particular applications described herein. Indeed, the novel lockdetector according to the invention may be disposed in a variety ofappropriate locations between a phase detector and VCO including beingimplemented in combination with a PLL loop filter. Nor is itparticularly important that a data recovery circuit or a decision enginebe coupled to the PLL in the manner depicted in the illustratedembodiments. It is sufficient that a PLL incorporate a lock detectoraccording to the invention that is capable of asserting “lock” upon theoccurrence of true phase lock, regardless of how “lock” is used bydown-stream processing circuitry.

[0038] Further, it will be understood by one having skill in the artthat the invention is not limited to use in connection with a PLLparticularly. From the foregoing description, it will be evident thatthe invention is suitable for use in connection with frequency lockdeterminations and might be incorporated in feedback-type control systemcircuitry of all varieties, in which the input conditions departsubstantially from strict steady state.

[0039] The invention, therefore is not limited to the particularembodiments, arrangements or applications disclosed, but is intended tocover any changes, modifications or adaptations that fall within thescope and spirit of the appended claims.

1. An interference rejection filter for removing undesirable frequencycomponents in a broadband signal disposed in a given frequency range,the filter comprising: a plurality of at least three filter stagesconnected in tandem, each filter stage having a multiplier with firstand second inputs and an output, an oscillator coupled to the firstinput, a baseband DC canceler stage coupling the output of each filterstage to the second input of the next filter stage except for the outputof the last filter stage; means for coupling the broadband signal to theinput of the first stage; a frequency conversion stage; and means forcoupling the output of the third last stage to the frequency conversionstage.
 2. The filter of claim 1, in which the frequency conversion stagereturns the broadband signal without the undesirable frequencycomponents to the given frequency range.
 3. The filter of claim 1, inwhich the filter stages each have a bandwidth that corresponds to thegiven frequency range.
 4. The filter of claim 1, in which themultipliers are complex multipliers.
 5. The filter of claim 1, in whichthe broadband signal is an HDTV signal.
 6. The filter of claim 1, inwhich the oscillator is a direct digital frequency synthesizer (DDFS) 7.The filter of claim 6, in which the oscillator of the first filter stagehas a frequency of 1.75 MHz.
 8. The filter of claim 1, in which theplurality of filter stages is three in number.
 9. The filter of claim 8,in which the oscillator of the first filter stage has a frequency of3.58 MHz.
 10. The filter of claim 9, in which the oscillator of thefirst filter stage has a frequency of 0.92 MHz.